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M69AW024BE
16 Mbit (1M x16) 3V Asynchronous PSRAM
FEATURES SUMMARY

SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIME: 60ns LOW STANDBY CURRENT: 70A DEEP POWER DOWN CURRENT: 10A COMPATIBLE WITH STANDARD LPSRAM TFBGA48 PACKAGE RoHS COMPLIANT (directive 2002/95/EC of the European Parliament)
Figure 1. Package
BGA
TFBGA48 (ZB) 6x8 mm
April 2005
1/25
M69AW024BE
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Upper Byte Enable (UB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Deep Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. Figure 5. Figure 6. Table 5. Table 6. Table 7. Figure 7. Figure 8. Figure 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read and Standby Modes AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Address Access after G Controlled Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . 14 UB/LB Controlled Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10.Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11.W Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 12.Write Enable and UB/LB Controlled, Byte Write AC Waveforms 1 . . . . . . . . . . . . . . . . . 18 Figure 13.Write Enable and UB/LB Controlled, Byte Write AC Waveforms 2 . . . . . . . . . . . . . . . . . 18 Figure 14.Write Enable and UB/LB Controlled, Byte Write AC Waveforms 3 . . . . . . . . . . . . . . . . . 19 Figure 15.Write Enable and UB/LB Controlled, Byte Write AC Waveforms 4 . . . . . . . . . . . . . . . . . 19 Table 9. Standby, Power-Down and Power-Up AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 16.Power-up Mode AC Waveforms - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 17.Power-up Mode AC Waveforms - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 18.Power-Down Entry ad Exit AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 19.Standby Mode Entry AC Waveforms, after Read or Write . . . . . . . . . . . . . . . . . . . . . . . 21 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 20.TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View . . . . 22 Table 10. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 22 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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M69AW024BE
SUMMARY DESCRIPTION
The M69AW024BE is a 16 Mbit (16,777,216 bit) CMOS memory, organized as 1,024,576 words by 16 bits, and is supplied by a single 2.7V to 3.3V supply voltage range. M69AW024BE is a member of STMicroelectronics PSRAM memory family, based on the one-transistor per-cell architecture. These devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area. However, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard Asynchronous SRAM Interface. The internal control logic of the M69AW024BE handles the periodic refresh cycle, automatically, and without user involvement. Write cycles can be performed on a single byte by using Upper Byte Enable (UB) and Lower Byte Enable (LB). The device can be put into standby mode using Chip Enable (E1) or in deep power down mode by using Chip Enable (E2). Power-Down mode achieves a very low current consumption by halting all the internal activities. Since the refresh circuitry is halted, the duration of the power-down should be less than the maximum period for refresh, if the user has not finished with the data contents of the memory.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A19 Address Input Data Input/Output Chip Enable, Power Down Output Enable Write Enable Upper Byte Enable Lower Byte Enable Supply Voltage Ground Not Connected (no internal connection)
VCC
DQ0-DQ15 E1, E2
20 A0-A19 W E1 E2 G UB LB M69AW024BE
16 DQ0-DQ15
G W UB LB VCC VSS NC
VSS
AI07406b
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M69AW024BE
Figure 3. TFBGA Connections (Top view through package)
1 2 3 4 5 6
A
LB
G
A0
A1
A2
E2
B
DQ8
UB
A3
A4
E1
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
A17
A7
DQ3
VCC
E
VCC
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
A19
A12
A13
W
DQ7
H
A18
A8
A9
A10
A11
NC
AI07409
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M69AW024BE
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Read and Write operations. Data Inputs/Outputs (DQ8-DQ15). The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UB) is driven Low. Data Inputs/Outputs (DQ0-DQ7). The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LB) is driven Low. Chip Enable (E1). When asserted (Low), the Chip Enable, E1, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. Chip Enable (E2). The Chip Enable, E2, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode. Output Enable (G). The Output Enable, G, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. Upper Byte Enable (UB). The Upper Byte Enable, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. Lower Byte Enable (LB). The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed. VSS Ground. The VSS Ground is the reference for all voltage measurements.
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M69AW024BE
Figure 4. Block Diagram
INTERNAL CLOCK GENERATOR ROW DECODER
ARBITRATION LOGIC REFRESH CONTROLLER VCC DYNAMIC MEMORY ARRAY
ADDRESS
DQ0-DQ7 DQ8-DQ15
E1 E2 G W LB UB VCC VSS POWER CONTROLLER CONTROL LOGIC
INPUT/OUTPUT BUFFER COLUMN DECODER
ADDRESS
AI07410
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M69AW024BE
OPERATION
Operational modes are determined by device control inputs W, E1, E2, LB and UB as summarized in the Operating Modes table (see Table 2.). Power On Sequence Because the internal control logic of the M69AW024BE needs to be initialized, the following power-on procedure must be followed before the memory is used: - Apply power and wait for VCC to stabilize - Wait tCHEL while driving both Chip Enable signals (E1 and E2) High - Activate the memory by driving Chip Enable (E1) Low. Read Mode The device is in Read mode when: - Write Enable (W) is High and - Output Enable (G) Low and - the two Chip Enable signals are asserted (E1 is Low, and E2 is High). The time taken to enter Read mode (tELQV, tGLQV or tBLQV) depends on which of the above signals was the last to reach the appropriate level. Data out (DQ15-DQ0) may be indeterminate during tELQX, tGLQX and tBLQX, but data will always be valid during tAVQV. Write Mode The device is in Write mode when - Write Enable (W) is Low and - Chip Enable (E1) is Low and - the two Chip Enable signals are asserted (E1 is Low, and E2 is High) one of Upper Byte Enable (UB) or Lower Byte Enable (LB) is Low, while the other is High. The Write cycle begins just after the event (the falling edge) that causes the last of these conditions to become true (tAVWL, tAVEL or tAVBL). The Write cycle is terminated by the earlier of a rising edge on Write Enable (W) or Chip Enable (E1). If the device is in Write mode (Chip Enable (E1) is Low, Output Enable (G) is Low, Upper Byte Enable (UB) or Lower Byte Enable (LB) is Low), then Write Enable (W) will return the outputs to high impedance within tWHDZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable (W), or for tDVEH before the rising edge of Chip Enable (E1), whichever occurs first, and remain valid for tBHDZ, tWHDZ, tEHDZ. Standby Mode The device is in Standby mode when: - Chip Enable (E1) is High and - Chip Enable (E2) is High. The input/output buffers and the decoding/control logic are switched off, but the dynamic array continues to be refreshed. In this mode, the memory current consumption, ISB, is reduced, and the data remains valid. Deep Power-down Mode The device is in Deep Power-down mode when: - Chip Enable (E2 is Low). -
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M69AW024BE
Table 2. Operating Modes
Operation Standby (Deselect) Output Disabled (2) Output Disabled (No Read) Upper Byte Read Lower Byte Read Word Read Upper Byte Write Lower Byte Write Word Write Power-down (3)
Note: 1. 2. 3. 4.
E2 VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL
E1 VIH VIL VIL VIL VIL VIL VIL VIL VIL X (1)
W X (1) VIH VIH VIH VIH VIH VIL VIL VIL X (1)
G X (1) VIH VIL VIL VIL VIL VIH VIH VIH X (1)
LB X (1) X (1) VIH VIH VIL VIL VIH VIL VIL X (1)
UB X (1) X (1) VIH VIL VIH VIL VIL VIH VIL X (1)
A0-A19 X (1) Note (4) Valid Valid Valid Valid Valid Valid Valid X (1)
DQ0-DQ7 Hi-Z Hi-Z Hi-Z Hi-Z Output Valid
DQ8DQ15 Hi-Z Hi-Z Hi-Z Output Valid Hi-Z
ICC ISB ICC ICC ICC ICC ICC ICC ICC ICC IPD
Data Retention Yes Yes Yes Yes Yes Yes Yes Yes Yes No
Output Valid Invalid Input Valid Input Valid Hi-Z Input Valid Invalid Input Valid Hi-Z
X = VIH or VIL. Output Disable mode should not be kept longer than 1s. Power-down mode can be entered from Stand-by state, and all DQ pins are in Hi-Z state. Can be either VIL or VIH but must be valid before Read or Write.
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M69AW024BE
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are Table 3. Absolute Maximum Ratings
Symbol IO TA TLEAD TSTG VCC VIO Output Current Ambient Operating Temperature Lead Temperature During Soldering Storage Temperature Core Supply Voltage Input or Output Voltage -55 -0.5 -0.5 Parameter Min -50 -30 Max 50 85
(1)
stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied.
Unit mA C C C V V
125 3.6 3.6
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
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M69AW024BE
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 4. Operating and AC Measurement Conditions
M69AW024BE Parameter Min VCC Supply Voltage1 Ambient Operating Temperature Load Capacitance (CL) Output Circuit Protection Resistance (R1) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Output Transition Timing Ref. Voltages Input Transition Time (t) between VIL and VIH(2) 0 to VCC VCC/2 VRL = 0.3VCC; VRH = 0.7VCC 5 2.7 -30 50 50 4 -60 Max 3.3 85 V C pF ns V V V ns Unit
Note: 1. All voltages are referenced to VSS. 2. The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 9.
Figure 5. AC Measurement Load Circuit
VCC/2
Figure 6. AC Measurement I/O Waveform
I/O Timing Reference Voltage R1 VCC VCC/2 OUT CL 0V
DEVICE UNDER TEST
Output Transition Timing Reference Voltage (1) VCC 0.7VCC 0.3VCC
AI07753c
0V
CL includes JIG capacitance
AI07222c
Note: 1. This waveform is given for Hi-Z and data transition AC parameters only (see Note 8. below Table 7., Read and Standby Modes AC Characteristics).
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M69AW024BE
Table 5. Capacitance
Symbol CIN COUT (1) Parameter Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 5 8 Unit pF pF
Note: 1. Outputs deselected.
Table 6. DC Characteristics
Symbol Parameter Test Condition VCC = 3.3V, VIN = VIH or VIL, E1 = VIL, E2 = VIH, IOUT = 0mA 0V VIN VCC 0V VOUT VCC VCC = 3.3V, VIN = VIH or VIL, E2 0.2V 3.1V VCC 3.3V, VIN 0.2V or VCC -0.2V, E1 VCC -0.2V and E2 VCC -0.2V), IOUT = 0mA 2.7V VCC 3.1V, VIN 0.2V or VCC -0.2V, E1 VCC -0.2V and E2 VCC -0.2V), IOUT = 0mA 2.7V VCC 3.3V 2.7V VCC 3.3V 3.1V VCC 3.3V, IOH = -0.5mA 2.7V VCC 3.1V, IOH = -0.5mA IOL = 1mA 0.8VCC -0.3 2.5 2.2 0.4 tRC/tWC = Min tRC/tWC = 1s -1 -1 Min Max 20 3.0 1 1 Unit mA mA A A
ICC1
(1)
Operating Supply Current
ILI ILO
Input Leakage Current Output Leakage Current Deep Power Down Current
IPD
10
A
100
A
ISB
Standby Supply Current CMOS
70
A
VIH (2) VIL (3) VOH VOL
Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
VCC + 0.2 0.2VCC
V V V V V
Note: 1. Average AC current, Outputs open, cycling at tAVAX (min). 2. Maximum DC voltage on inputs and I/O pins is VCC + 0.2V. During voltage transitions, data inputs may overshoot to VCC + 1.0V for a period of up to 5ns. 3. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, data inputs may overshoot to VSS + 1.0V for a period of up to 5ns.
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M69AW024BE
Table 7. Read and Standby Modes AC Characteristics
M69AW024BE Symbol Alt. Parameter Min tAVAX, tELEH
(1,2)
-60 Max 1000 60 40 60 30 5 5 0 0 20 20 20 -5 10 10 -5 -5 10 10 1000
Unit
tRC tCE tOE tAA tBA tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tAX tCHAH tOHAH tWHOL tCP
Read Cycle Time Chip Enable Access Time Output Enable Access Time Address Access Time LB, UB Low to Output Valid Output Hold Time after Chip Enable Low Chip Enable Low to Output Low-Z Output Enable Low to Output Low-Z LB, UB Low to Output Low-Z Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z LB, UB High to Output Hi-Z Address Set-up Time to Chip Enable Low Address Valid to Output Enable Low Address Invalid Time Chip Enable High to Address Hold Time Output Enable High to Address Hold Time Write Enable High to Output Enable Low (Read Operations) Chip Enable High Pulse Width
70
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tELQV(3) tGLQV(3) tAVQV(3,5) tBLQV(3) tAXQX, tGHQX, tBHQX, tEHQX
(8)
tELQX(4,8) tGLQX(4,8) tBLQX(4,8) tEHQZ(8) tGHQZ(8) tBHQZ(8) tAVEL tAVGL tAXAV(5) tEHAX(6) tGHAX tWHGL(7) tEHEL
Note: 1. The maximum value of this timing is applicable if E1 is kept Low with addresses unchanged.If needed by the system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Addresses should not be changed during tAVAX(min). 3. These parameters are measured according to the conditions on input and output timing reference voltage shown on Figure 6., AC Measurement I/O Waveform. 4. The output load capacitance is 5pF without any other load. 5. These timings are given for E1 Low. 6. tAVAX(min) must be satisfied. 7. If the current value of tWHGL is lower than the minimum value given in the above table, tAVQV during the following Read operation may increase by tWHGL(current) - tWHGL(min). 8. All timings are measured according to the conditions for output transition timing reference voltage shown on Figure 6., AC Measurement I/O Waveform.
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M69AW024BE
Figure 7. Read Mode AC Waveforms
tELEH A0-A19 tAVEL tELQV E1 tEHEL tGLQV G tBLQV LB, UB tBLQX tGLQX tELQX DQ0-DQ15 VALID DATA OUTPUT
AI09936
ADDRESS VALID
VALID tAVEL tEHAX
tEHQZ
tGHQZ
tBHQZ tEHQX
Note: E2 = High and W = High.
Figure 8. Address Access after G Controlled Read AC Waveforms
tAVAX A0-A19 ADDRESS VALID tAVQV E1 tAVGL G tGLQV tAXAV
tAVAX ADDRESS VALID tAVQV tAXAV
tGHQX UB, LB tGLQX DQ0-DQ15 tAXQX DATA OUT DATA OUT
AI09937
tGHQZ
Note: 1. E2 = High and W = High. 2. During the two consecutive Read operations, the Output Enable signal, G, can either remain Low, or be toggled.
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M69AW024BE
Figure 9. UB/LB Controlled Read AC Waveforms
tAXAV A0-A19 tAVQV E1 Low tAVAX ADDRESS VALID tAXAV
G LB
Low tBLQV tBLQV
UB
tBHQZ
tBLQV
tBHQZ
tBLQX DQ0-DQ7
tBHQX VALID DATA OUT
tBLQX
tBHQX VALID DATA OUT tBHQZ
tBLQX DQ8-DQ15
tBHQX VALID DATA OUTPUT
ai09938b
Note: E2 = High and W = High.
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Table 8. Write Mode AC Characteristics
M69AW024BE Symbol Alt. Parameter Min tAVAX, tELAX(1,2) tAVEL, tAVBL, tAVWL(2) tELEH(3) tWLBH, tWLWH(3) tBLWH, tBLBH(3) tBHWL(4) tWHBL(5) tWHAX, tEHAX, tBHAX(6) tEHEL tWHWL tBHBL tDVEH, tDVWH, tDVBH tEHDZ, tWHDZ, tBHDZ, tGHDZ tGHEL(7) tGHAV(8) tBLBH2 tWC tAS tCW tWP tBW tBS tBH tWR tCP tWHP tBHP tDS tDH tOHCL tOES tBWO Chip Enable Write Cycle Time 70 -60 Max 1000 ns Unit
Address Set-up Time to Chip Enable Low Chip Enable Write Pulse Width Write Enable Write Pulse Width
0 45 45
ns ns ns
LB, UB Pulse (Write Operation) LB, UB Byte Masking Set-up Time LB, UB Hold Time Write Recovery Time Chip Enable High Pulse Write Enable High Pulse LB, UB High Pulse Data Set-up Time Data Hold Time Output Enable High to Chip Enable Low Set-up Time Output Enable Set-up Time LB, UB Low to LB, UB High for Page Access
45 -5 -5 0 10 10 10 15 0 -5 0 30 1000 1000
ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. The maximum value of this timing is applicable if E1 is kept Low without any address change. If needed by system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Minimum value must be equal to or greater than the sum of the write pulse (tELEH, tWLBH or tBLBH and the write recovery time tWHAV. 3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last. 4. Applicable to Byte Masking only. Byte Masking set-up time is defined from the falling edge of E1 or W whichever occurs last. 5. Applicable to Byte Masking only. Byte Masking hold time is defined from the rising edge of E1 or W whichever occurs first. 6. Write recovery is defined from the rising edge of E1, W, or LB/UB, whichever occurs first. 7. If G is Low after tGHEL(min), the read cycle is initiated. In other words, G must be brought High within tGHEL (min) after E1 is brought Low. Once the read cycle is initiated, new write pulse should be input after tAVAX or tELEH minimum value. 8. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before new address valid. Once the read cycle is initiated, new write pulse should be input after tAVAX or tELEH minimum value.
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Figure 10. Write AC Waveforms
tELAX A0-A19 ADDRESS VALID tEHAX,tWHAX, tBHAX tAVEL E1 tEHEL tAVWL W tBHAX tAVBL LB, UB tGHEL G tDVEH tDVWH tDVBH VALID DATA INPUT
ai09939
ADDRESS VALID
tELEH
tAVEL
tWLWH
tAVWL
tWHWL tAVBL
tBLWH
tBHBL tEHDZ tWHDZ tBHDZ
DQ0-DQ15
Note: 1. E2 must be High during the Write cycle.
Figure 11. W Controlled, Write AC Waveforms
tAXAV A0-A19 tGHAX E1 Low tAVWL W tWHWL LB, UB tGHAV G tDVWH tGHDZ DQ0-DQ15 VALID DATA INPUT tWHDZ tDVWH VALID DATA INPUT
AI09940
tAVAX ADDRESS VALID
tAVAX ADDRESS VALID
tWHAX tWLWH tAVWL tWLWH tWHAX
tWHDZ
Note: 1. E2 must be High during the Write cycle.
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Figure 12. Write Enable and UB/LB Controlled, Byte Write AC Waveforms 1
tAVAX A0-A19 ADDRESS VALID tAXAV E1 Low tAVWL W tBHAX tWHWL LB tBHWL tBHWL tWHBL UB tDVBH DQ0-DQ7 VALID DATA INPUT tDVBH DQ8-DQ15
Note: 1. E2 and G must be High during the Write cycle.
tAVAX ADDRESS VALID
tWLBH
tAVWL
tWLBH
tBHAX tWHBL
tBHDZ
tBHDZ VALID DATA INPUT
AI09941
Figure 13. Write Enable and UB/LB Controlled, Byte Write AC Waveforms 2
tAVAX A0-A19 ADDRESS VALID tAVAX ADDRESS VALID
E1
Low tAVBL tBLWH tWHWL
W tWHAX tBHWL LB tBHWL tWHBL UB tDVWH DQ0-DQ7 VALID DATA INPUT tDVWH DQ8-DQ15
Note: 1. E2 and G must be High during the Write cycle.
tWHAX tWHBL
tAVBL tBLWH
tWHDZ
tWHDZ VALID DATA INPUT
AI09942
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M69AW024BE
Figure 14. Write Enable and UB/LB Controlled, Byte Write AC Waveforms 3
tAVAX tAVAX
A0-A19 E1 Low tAVBL W
ADDRESS VALID tAXAV tBLBH tWHWL
ADDRESS VALID
tBHAX tBHWL LB tBHWL tAVBL tWHBL UB tDVBH DQ0-DQ7 VALID DATA INPUT tBVWH DQ8-DQ15
Note: 1. E2 and G must be High during the Write cycle.
tWHBL
tBLBH
tBHAX
tBHDZ
tBHDZ VALID DATA INPUT
AI09943
Figure 15. Write Enable and UB/LB Controlled, Byte Write AC Waveforms 4
tAVAX A0-A19 E1 Low ADDRESS VALID tAVAX ADDRESS VALID
W tBHAX tAVBL LB tAVBL tDVBH DQ0-DQ7 VALID DATA INPUT tBHAX tBLBH UB tBHBL tDVBH DQ8-DQ15 VALID DATA INPUT tBHDZ tDVBH VALID DATA INPUT tBHDZ tAVBL tBLBH2 tBHBL tBHDZ tDVBH VALID DATA INPUT tBLBH2 tBLBH tBHAX tBHDZ tBLBH tAVBL tBLBH tBHAX
AI09944
Note: 1. E2 and G must be High during the Write cycle.
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Table 9. Standby, Power-Down and Power-Up AC Parameters
M69AW024BE Symbol Alt. Parameter Min tCLEL tELCH tCHEL(1) tEHCH tEHGH tEHWH(2) t(3) tEHCH2
Note: 1. 2. 3. 4.
-60 Max
Unit
tCSP tC2LP tCHH tCHS tCHOX tCHWX t tC2LH
E2 Low Setup Time for Power Down Entry E2 Low Hold Time after Power Down Entry E1 High Hold Time following E2 High after Power-Down Exit E1 High Hold Time following E2 High after Power-Up E1 High Setup Time following E2 High after Power-Down Exit E1 High to G Invalid Time for Standby Entry E1 High to W Invalid Time for Standby Entry Input Transition Time Power-Up Time
10 80 300 0 10 10 1 50 25
ns ns s ns ns ns ns s
Applicable both to Power-Down and Power-Up. Some data might be written into any address location if tEHWL (min) is not satisfied. The Input Transition Time used in AC measurements is 5ns. TBD = to be defined.
Figure 16. Power-up Mode AC Waveforms - 1
E1 tEHCH tEHCH2 E2 tCHEL
VCC 0V
VCC min
AI07740b
Note: tEHCH2 is defined from VCC reaching VCC(min).
Figure 17. Power-up Mode AC Waveforms - 2
E1 tEHEL E2
VDD
VDDmin
AI09945
Note: tCHEL is defined from VCC reaching VCC(min) and applicable both for E1 and E2 signals.
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M69AW024BE
Figure 18. Power-Down Entry ad Exit AC Waveforms
E1 tEHCH E2 tCLEL DQ0-D15 Hi-Z tELCH tCHEL
Power-Down Entry
Power-Down Mode
Power-Down Exit
AI09946
Note: The Power-Down mode timing can also be used as a Reset timing if the Power-up mode timing cannot be satisfied.
Figure 19. Standby Mode Entry AC Waveforms, after Read or Write
E1 tEHGH G High W
E1 High G tEHWH
W
Active (Read)
Standby
Active (Write)
Standby
AI07741b
Note: Both tEHGH and tEHWH define the earliest entry timing for Standby mode. If one of these timings is not satisfied, it takes a tAVAX(min) delay to enter Standby mode from E1 rising edge.
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M69AW024BE
PACKAGE MECHANICAL
Figure 20. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View
D FD FE SD D1
SE BALL "A1" E E1 ddd
e e A A1 b A2
BGA-Z26
Note: Drawing is not to scale.
Table 10. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 8.000 5.250 0.750 1.125 1.375 0.375 0.375 7.900 - - - - - - 6.000 3.750 0.350 5.900 - 0.260 0.900 0.450 6.100 - 0.100 8.100 - - - - - - 0.3150 0.2067 0.0295 0.0443 0.0541 0.0148 0.0148 0.3110 - - - - - - 0.2362 0.1476 0.0138 0.2323 - Min Max 1.200 0.0102 0.0354 0.0177 0.2402 - 0.0039 0.3189 - - - - - - Typ Min Max 0.0472 inches
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M69AW024BE
PART NUMBERING
Table 11. Ordering Information Scheme
Example: Device Type M69 = 1T/1C Memory Cell Architecture Mode A = Asynchronous Operating Voltage W = 2.7 to 3.3V Array Organization 024 = 16 Mbit (1M x16) Option 1 B = 2 Chip Enable Option 2 E = E die Speed Class 60 = 60ns Package ZB = TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch Temperature Range 8 = -30 to 85 C Packing Option F = RoHS Compliant Package, Tape & Reel Packing M69AW024BE 60 ZB 8 F
The notation used for the device number is as shown in Table 11.. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest STMicroelectronics Sales Office.
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M69AW024BE
REVISION HISTORY
Table 12. Document Revision History
Date 28-Jun-2004 29-Jun-2004 Rev. 0.1 0.2 First Issue Table 11., Ordering Information Scheme updated. tEHQX added in Table 7., Read and Standby Modes AC Characteristics. tGHDZ and tBHDZ added in Table 8., Write Mode AC Characteristics. Figure 19., Standby Mode Entry AC Waveforms, after Read or Write updated. RoHS Packing option added in FEATURES SUMMARY and Table 11., Ordering Information Scheme. TLEAD parameter added in Table 3., Absolute Maximum Ratings Figure title modified and Note 2 added below Figure 8. Revision Details
22-Mar-2005
1.0
05-Apr-2005
2.0
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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